The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing electromigration in copper interconnect lines by doping their surfaces with a barrier material using wet chemical methods.
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-xcexcm to 0.25-xcexcm) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractory metals. Despite aluminum""s (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.
However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.1 These problems have instigated further research into the formulation of barrier materials for preventing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices particularly having aluminum-copper alloy interconnect lines, the industry has been investigating the use of various barrier materials such as titanium-tungsten (TiW) and titanium nitride (TiN) layers as well as refractory metals such as titanum (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), and their silicides.2 Although the foregoing materials are adequate for Al interconnects and Alxe2x80x94Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. Further, though CVD and PECVD have been conventionally used for depositing secondary metal(s) on a primary metal interconnect surface, neither technique provides a cost-effective method of forming a copper-zinc alloy on a Cu interconnect surface. Therefore, a need exists for a low cost and high throughput method of reducing electromigration in a dual-inlaid copper interconnect line by filling a via with a graded copper-zinc (Cuxe2x80x94Zn) alloy electroplated on a copper (Cu) surface from a stable chemical solution, and by controlling and ordering the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance.
1Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 3rd Ed., p. 397 (1997).
2Id., at 392.
Accordingly, the present invention provides a method of reducing electromigration in a dual-inlaid copper interconnect line by filling a via with a graded Cu-rich (e.g., approximately 99.8 at. % to approximately 98 at. %) copper-zinc (Cuxe2x80x94Zn) alloy electroplated on a copper (Cu) surface from a stable chemical solution, and by controlling and ordering the Zn-doping thereof (e.g., approximately 0 at. % to approximately 4 at. %, preferably approximately 0 at. % to approximately 1 at. %), which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The present method involves filling the via by electroplating the Cu surface, such as a Cuxe2x80x94Zn alloy seed layer and a partial thickness plated Cu layer, into a unique nontoxic aqueous chemical electroplating solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants, thereby forming an electroplated Cuxe2x80x94Zn alloy fill having some degree of oxygen (O) concentration, wherein the Zn-doping is controllable by varying the electroplating conditions; and annealing the Cuxe2x80x94Zn alloy fill formed on the Cu surface in an environment such as vacuum, nitrogen (N2), hydrogen (H2), formine (N2H2), or mixtures thereof for reducing the O-concentration in the alloy fill, for modifying the grain structure of the graded Cuxe2x80x94Zn alloy fill as well as of the underlying Cu surface, and for forming a mixed Cuxe2x80x94Zn/Cu interface, thereby forming the dual-inlaid interconnect structure. The present invention further provides a particular electroplating method which controls the parameters of Zn concentration, pH, temperature, and time in order to form a graded reduced-oxygen copper-zinc (Cuxe2x80x94Zn) alloy fill on a cathode-wafer surface such as a copper (Cu) surface for reducing electromigration in the device by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.
More specifically, the present invention provides a method of fabricating a semiconductor device, having a graded reduced-oxygen copper-zinc (Cuxe2x80x94Zn) alloy fill formed on a copper (Cu) surface by electroplating the Cu surface in a chemical solution, generally comprising the steps of: providing a semiconductor substrate having a Cu surface (e.g., a Cuxe2x80x94Zn alloy seed layer), the Cu surface having been formed by CVD, PVD, PECVD, ALD, or electroplating, an optional barrier layer, and an optional underlayer formed in a via; providing a chemical solution; immersing the Cu surface in the chemical solution, thereby forming a graded Cuxe2x80x94Zn alloy fill on the Cu surface in the via, wherein the electroplating parameters such as current density, solution flow rate (hydrodynamic conditions), temperature, and spacing between the anode and the wafer (current density is variable by mechanical adjustment) are varied in situ to effect the desired Zn-content gradient in the alloy fill; rinsing the graded Cuxe2x80x94Zn alloy fill in a solvent; drying the graded Cuxe2x80x94Zn alloy fill under a gaseous flow; annealing the graded Cuxe2x80x94Zn alloy fill formed on the Cu surface, thereby forming a graded reduced-oxygen Cuxe2x80x94Zn alloy fill; planarizing the graded reduced-oxygen Cuxe2x80x94Zn alloy fill, the Cu surface, the optional barrier layer, and the optional underlayer, thereby completing formation of a Cuxe2x80x94Zn alloy dual-inlaid interconnect structure; and completing formation of the semiconductor device.
By electroplating this graded Cuxe2x80x94Zn alloy fill in the via and on the cathode-wafer surface, such as a Cu surface (e.g., Cuxe2x80x94Zn alloy seed layer), using a stable chemical solution in the prescribed concentration ranges and by subsequently annealing the graded Cuxe2x80x94Zn alloy fill electroplated on the Cu surface, the present invention improves Cu interconnect reliability, enhances electromigration resistance, improves corrosion resistance, and reduces manufacturing costs. In particular, the present invention chemical solution is advantageous in that it facilitates formation of an acceptable graded Cuxe2x80x94Zn alloy fill over a wide range of bath compositions while the subsequent annealing step removes undesirable oxygen impurities from the formed alloy fill. The desirable Zn content gradient in the graded Cuxe2x80x94Zn alloy fill, preferably in a range of approximately 0 at. % to approximately 4 at. %, preferably in a range of approximately 0 at. % to approximately 1 at. %, determined by X-Ray Photoelectron Spectroscopy (XPS) or Auger Electron Spectroscopy (AES), is controllable by varying the electroplating conditions and/or the bath composition. By so controlling and ordering the Zn-doping, the present method Zn content gradient better balances high electromigration performance against low resistivity requirements. Additionally, the Cu surface (e.g., Cuxe2x80x94Zn alloy seed layer), being formed by a technique such as electroless deposition, ion metal plasma (IMP), self-ionized plasma (SIP), hollow cathode magnetron (HCM), chemical vapor deposition (CVD), and atomic layer deposition (ALD), is enhanced by the graded Cuxe2x80x94Zn alloy fill and is prevented from etching by the high pH value (i.e., basic) of the chemical solution from which the graded alloy fill is formed.
Further advantages arise from the present invention""s superior fill-characteristics. The present Cuxe2x80x94Zn electroplating solution facilitates better filling of the via on an interconnect, especially for feature sizes in a dimensional range of approximately 0.2 xcexcm to approximately 0.05 xcexcm, thereby lowering the resistance of the formed Cuxe2x80x94Zn alloy fill (e.g., in a resistance range of approximately 2.2 xcexcxcexa9xc2x7cm to approximately 2.5 xcexcxcexa9xc2x7cm for approximately 1 at. % Zn content in a Cuxe2x80x94Zn alloy fill, as deposited). Further, the filling capability is enhanced by three beneficial characteristics of the present invention: (1) the instant chemical solution does not etch copper or a Cuxe2x80x94Zn alloy seed layer; (2) the introduction of Zn into the graded alloy fill as well as onto the Cu interconnect improves both step coverage and nucleation; and (3) a variety of organic additives, such as polyethylene glycol (PEG), organo-disulfides, and organo-chlorides, are compatible and may be included in the instant chemical solution for further enhancing the fill profile and grain structure. The present Cuxe2x80x94Zn electroplating solution provides a desirably low Zn content gradient in a Cu alloy interconnect (e.g., in a concentration range of approximately 0.2 at. % to approximately 1.0 at. %) which also imparts (1) a de minimis increase in electrical resistance as well as (2) a maximum improvement in electromigration resistance. The present chemical solution can also provide a desirably low Zn content gradient in a Cu film, wherein the Zn content gradient may be ordered by varying the deposition parameters as well as by modifying the bath composition.